With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The use of metal gates within metal-oxide-semiconductor (MOS) transistors has developed with respect to both planar and three dimensional devices such as FinFET devices. Gate structures including a high-k dielectric layer and one or more metal layers that function as gate electrodes have been implemented. Replacement gate techniques, which are sometimes called “gate last” techniques, involve forming a “dummy” or sacrificial gate structure. The sacrificial gate structure remains present during various other fabrication processes, such as the formation of source/drain regions and possible annealing steps. The sacrificial gate structure is then removed to define a gate cavity where the desired actual gate structure is formed. As middle-of-line (MOL) dimensions continue to decrease, currently employed metallization schemes that include the use of some metal fill materials such as tungsten (W) may not be able to meet resistance targets for future technology nodes. The high resistance associated with tungsten is a result of the need for thick titanium nitride (TiN) liners to prevent fluorine (F) diffusion and poor tungsten gap fill (seams/voids).
In some replacement gate processes, disposable gate level layers are deposited on a semiconductor substrate as blanket layers, i.e., as unpatterned contiguous layers. The disposable gate level layers can include, for example, a vertical stack of a disposable gate dielectric layer, a disposable gate material layer, and a disposable gate cap dielectric layer. The disposable gate dielectric layer can be, for example, a layer of silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the disposable gate dielectric layer can be from 1 nm to 10 nm, although lesser and greater thicknesses can also be employed. The disposable gate material layer includes a material that can be subsequently removed selective to the dielectric material of a planarization dielectric layer to be subsequently formed. For example, the disposable gate material layer can include a semiconductor material such as a polycrystalline semiconductor material or an amorphous semiconductor material. The thickness of the disposable gate material layer can be from 30 nm to 300 nm, although lesser and greater thicknesses can also be employed. The disposable gate cap dielectric layer can include a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the disposable gate cap dielectric layer can be from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. Any other disposable gate level layers can also be employed provided that the material(s) in the disposable gate level layers can be removed selective to a planarization dielectric layer to be subsequently formed.
The disposable gate level layers are lithographically patterned to form disposable gate structures. Specifically, a photoresist is applied over the topmost surface of the disposable gate level layers and is lithographically patterned by lithographic exposure and development. The pattern in the photoresist is transferred into the disposable gate level layers by an etch process, which can be an anisotropic etch such as a reactive ion etch (RIE). The remaining portions of the disposable gate level layers after the pattern transfer form the disposable gate structures.
Disposable gate stacks may include, for example, first disposable gate structures formed over a first body region in a first device region (for example, an nFET region) and second disposable gate structures formed over a second body region in a second device region (for example, a pFET region). The first disposable gate structures can be a stack of a first disposable gate dielectric and gate material portions and first disposable gate cap portions, and the second disposable gate structures can be a stack of a second disposable gate dielectric and second disposable gate material portions and a second disposable gate cap portion. The first and second disposable gate cap portions are remaining portions of the disposable gate cap dielectric layer, the disposable gate material portions are remaining portions of the disposable gate material layer, and the disposable gate dielectric portions are remaining portions of the disposable gate dielectric layer.
Source/drain extension regions are formed after the disposable gate structures have been completed. For example, selected dopants can be implanted into portions of the first body region that are not covered by the first disposable gate structures to form source/drain extension regions. Similarly, other selected dopants can be implanted into portions of the second body region that are not covered by the second disposable gate structures. Gate spacers can be formed on sidewalls of each of the disposable gate structures, for example, by deposition of a conformal dielectric material layer and an anisotropic etch. Ion implantations can be employed to form source regions and drain regions for some devices. For example, dopants can be implanted into portions of the body regions that are not covered by the disposable gate structures and spacers.
A planarization dielectric layer is deposited over the semiconductor substrate, the disposable gate structures, and the gate spacers. The planarization dielectric layer may include a dielectric material that can be planarized, for example, by chemical mechanical planarization (CMP). For example, the planarization dielectric layer can include a doped silicate glass, an undoped silicate glass (silicon oxide), and/or porous or non-porous organosilicate glass. The planarization dielectric layer is planarized above the topmost surfaces of the disposable gate structures.
The disposable gate structures are removed by at least one etch. The at least one etch can be a recess etch, which can be an isotropic etch or anisotropic etch. The removal of the disposable gate structures can be performed employing an etch chemistry that is selective to the gate spacers and to the dielectric materials of the planarization dielectric layer. Cavities are formed from the spaces remaining after the disposable gate structures are removed. The semiconductor surfaces above the channel regions of the substrate can be physically exposed at the bottoms of the gate cavities, though native oxide layers may be present. The gate cavities are laterally enclosed by the gate spacers that were formed on the sidewalls of the disposable structures.
Replacement gate structures are formed in the gate cavities. Replacement gate structures are formed by replacement of the disposable structures and overly channel regions of field effect transistors having permanent gate structures. A gate dielectric and a gate electrode are formed within each of the gate cavities. A gate dielectric layer can be deposited on the bottom surface and sidewall surfaces of each gate cavity and over the planarization dielectric layer. The gate dielectric layer can be deposited as a contiguous gate dielectric layer that contiguously covers all top surfaces of the planarization dielectric layer and all inner sidewall surfaces of the gate spacers. The gate dielectric layer can be a high dielectric constant (high-k) material layer having a dielectric constant greater than 3.9. Gate dielectric layers can include a dielectric metal oxide, which is a high-k material containing a metal and oxygen. Dielectric metal oxides can be deposited by methods well known in the art including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source misted chemical deposition (LSMCD), and atomic layer deposition.
The replacement gate structures can include gate electrodes having different compositions in different regions of the substrate. For example, a first work function material layer can be deposited on the gate dielectric layers in one region and a second work function material can be deposited on the gate dielectric layers in a second region. A conductive material layer can be deposited on the work function material layers. The conductive material layer can include a conductive material deposited by physical vapor deposition, chemical vapor deposition, and/or electroplating. The conductive material layer can be an aluminum layer, a tungsten layer, an aluminum alloy layer, or a tungsten alloy layer. Tungsten can be deposited by chemical vapor deposition. Portions of the gate conductor layer, the work function material layers, and the gate dielectric layers are removed from the planarization dielectric layer by a planarization process. Replacement gate structures are thus formed, which include gate conductor layers, work function material layers, and gate dielectric layers.
Self-aligned contacts facilitate alignment during fabrication of integrated circuit devices having small dimensions. Such contacts have been formed by depositing metals such as aluminum and tungsten in trenches formed in dielectric materials while avoiding electrical contact with metal gate material. Self-aligned contacts can accordingly be formed within a metal gate process while preventing gate to contact shorts. Metal deposition processes have been developed for filling vias etched within multiple layers of electrically insulating material. The vias are filled with an electrically conducting metallization that preferably minimizes voids within the vias or other pathways while providing low resistance contact to active silicon device regions. Barrier layers, which sometimes include multiple layers, are further provided to prevent penetration of metallization components into the silicon and active device contact regions.